Failures during manufacturing and assembly or in the field caused by charged device model (CDM) type ESD events are a serious concern for IC design teams.
CDM failures are generally caused by charge build-up on device packages, which capacitively charge large internal nets, such as GND or VSS. Once a device pin contacts a current path, the charged internal net can discharge through triggered devices to the pin. ESD protection devices allow this to occur harmlessly. However, if the ESD protection network does not work as intended, dangerously high voltages and currents can affect protected devices in the IC. The only reliable method of determining if ESD protections will be effective is using simulation. However, conventional circuit simulation is difficult to set up, too slow and provides hard to interpret results for CDM events. Magwel has developed a simulation based solution specifically designed to address CDM discharge events.
In this seminar, you will learn how Magwel’s CDMi efficiently models the complex behavior of a CDM event in an integrated circuit. CDMi uses vf-TLP models in conjunction with 3D solver based resistive network extraction and dynamic simulation to predict device triggering. The results are comprehensive reporting of discharge event voltage and current flows. We will show how CDMi enables CDM ESD signoff before tape out to ensure high product quality and improved yields.