Heat dissipation is always a major concern in the design of power management integrated circuits. Overheating can lead to thermal runaway, where the current in a portion of a large PowerMOS will actually increase dramatically as a result of local heating. This can create a vicious cycle that may lead to device failure. Package design plays a big role in managing thermal issues. In a rare favorable confluence, the development of copper clip (Cu-clip) to replace wire bond not only helped reduce Rdson, but also made a big improvement in thermal conduction off of the die. Even though Cu-clip offers improved device performance and reliability, there are still pitfalls that need to be avoided during the design process.
Designing packaging is always a game of trade-offs. We have seen a growing requirement to look at the combination of the package and design layout to perform a sign-off level electro- thermal analysis. If, for instance, the Cu-clip does not completely cover the PowerMOS device, unexpected heating may occur. A full post-package design analysis is the only way to ensure that there will be no adverse and unanticipated effects once the circuit is operated under load in its actual environment.
To illustrate the consequences of overlooking electro-thermal effects in the finished chip, we have assembled a test case that shows the risk of thermal runaway after the package is included. The test case includes the full layout for the silicon and the enclosing package for a VDMOS power device. In Figure 1 below you can see that the package design uses a Cu-clip that does not completely cover the power device on the die.
Figure 1 – 3D view of device showing Cu-clip over a portion of the die (blue).
To simulate this design, we use Magwel’s PTM-ET for concurrent electro-thermal analysis. PTM-ET meshes the source, gate and drain metallization using the foundry SPICE model for the intrinsic device which includes a temperature coefficient. At each time step the full set of electric and thermal equations are simultaneously solved to determine state of the device. The information reported includes voltage and current density at every point on the die.
The applied gate stimulus in PTM-ET for our example uses a VCVS which is driven by the voltage differential between Vd and Vref, resulting in 3A load current. Our simulation covers 42 time steps over the first 1000 ms of operation. The sequence below shows the heat concentrating at the left edge where there is no coverage of the die by the Cu-clip. By 300 ms the temperature at the hot spot has reached nearly 600 C, hot enough to cause chip failure.
Figure 2 – Temperature on the die at 80ms, 100ms and 300ms
What is even more interesting is the corresponding current field view provided by PTM-ET at the 300 ms mark, shown below in Figure 3 next to the top view of the Cu-clip and die.
Figure 3 – Current at 300ms and top view of Cu-clip over die
The peak current in this image is 0.0778 mA/um compared to only 0.000843 mA/um farthest from the hot spot, nearly a 100x difference. As a result, we see that the area not covered by the Cu-clip is vulnerable to increased temperature and commensurately higher current levels. Even at levels below device failure, non-uniform current conduction can lead to electro-migration issues and affect operational characteristics such as Rdson. With Ids concentrated in a smaller metal area much of the device performance is compromised.
As shown above Magwel’s PTM-ET can merge in the design of packaging elements and uses their thermal properties to predict thermal flux through the bottom and top of the die. It is also possible to add in heatsink and board thermal elements, including heating from nearby packages.
PTM-ET’s solver based resistance extraction assures that accurate R values are used in the simulation. This is especially important where there are wide metals and non-uniform current flows. Using a single solver for the combined electro-thermal equations provides a faster and more accurate result for each time step. This is extremely important because each new time step relies on the accuracy of the previous time step.
PTM-ET is built on the PTM platform from Magwel for power transistor modeling. PTM itself provides steady state Rdson and power-per-layer. Its built-in field viewer visualizes V, I, current density, EM violations and power dissipation over the entire device. Built in layout editing helps designers quickly experiment with changes in metallization and bondpad size and placement.