Need an effective CDM sign-off strategy?
Magwel has developed a breakthrough CDM simulation solution that computes IR-drop and current densities during CDM events. It also checks for voltage-stress on both I/O and core protected devices.
Is decoupled electrical and thermal analysis leading to thermal runaway issues?
Learn how combined concurrent electro-thermal analysis on PowerMOS devices can save designs from overheating failures.
Want to work faster while making and verifying ESD violation fixes?
This article on SemiWIki explains how fixes for ESD issues can be tested without looping back and forth between your layout editor and the ESD simulator
Need to understand detailed dynamic switching behavior inside of PowerFETs?
See this animation of PTM-TR results for a power converter MosFET pair using Magwel generated Fast3D models co-simulated with Spectre®
Snapback behavior determines ESD protection effectiveness
Read about how proper modeling of snapback devices and parallel discharge paths can lead to success or failure in properly predicting ESD protection network effectiveness.
Worried about current crowding during switching transients in power devices that could cause reliability issues in your designs?
Magwel’s PTM-TR™ is a transient switching analysis solution for device source, gate and drain nets in power and converter circuits. The power device can be simulated during circuit operation to ensure current crowding hot spots are not going to lead to device failures.
Struggling to reduce VCC-min on SRAM’s?
Learn how Magwel® RNi™ can help reduce costly VCC connection errors that contribute to a higher than necessary VCC-min.
Want to know the best location for replica and sense devices in power transistors?
Read how PTM-ET™ can help locate hot spots in power devices and provide assurance that replicas and sense devices are properly placed.
Having difficulty with shoot-through current in your DC-to-DC converter designs?
Read on SemiWiki.com how Magwel’s PTM® family of power transistor modeling tools can help optimize dead-time and shoot-through current in multi-transistor configurations.
Do you have ESD failures due to parasitic currents in the substrate?
The latest release of ESDi® provides more accurate I/R information on all discharge paths during an ESD event. Its simulation based approach uses TLP data to include linear and snap back behavior.
Concerned about IR Drop and Electro Migration on power and ground nets?
Our newest product, RNi™, shows resistance between any pin and any point on the network. Its GUI can help make debugging power and ground network issues fast and easy.
Contact us to receive a brochure or white paper on ESD analysis and Electrothermal modeling of power devices.