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Magwel offers breakthroughs in HBM ESD analysis with its revolutionary ESDi-XL product:
- Checks for over-stresses on core devices
- Schematic-based topological and tore checks for early analysis
- Layout-based checks for more accurate analysis at later stages of the design process.
- Supports multiple power domains and pad grouping
- Accurately extracts large power/ground nets
- Simulates currents inside ESD cells, including during snap back.
- Reports bus resistance, voltage-stress, electro-migration violations, and device burnout
- Checks for missing or undersized vias & current crowding in metal and vias
Magwel offers a breakthrough in ESD analysis with its revolutionary ESDi-XL product. ESDi-XL thoroughly analyzes all of the pad2pad combinations in a design. Chips with large numbers of pins are analyzed extremely quickly using parallel processing and optimizations that preserve accuracy and boost speed.
ESDi-XL not only isolates and extracts the ESD network – it also identifies overstresses on core devices. Sophisticated Electronic Rule Checks (ERCs) are also performed to help remove ESD weaknesses.
ESDi-XL uses extraction and simulation engines specifically designed for ESD verification to analyze the circuit layout and protection devices. It does a better job than conventional circuit simulators because it handles snapback device models.
ESDi-XL analyzes parallel ESD device triggering for accurate current values on all discharge paths using precise extracted parasitics for the full ESD protection network.
ESDi-XL also can run on schematics only for detection of ESD issues early in the product design cycle. This mode of operation is a game changer because problems can be solved long before layout is complete.
Here is how ESDi-XL has helped some our customers:
“It’s the workhorse tool now for ESD reviews”
“A junior engineer using ESDi is able to do the work of a senior ESD engineer”
“About 50% of the designs that come through the team get sent back to design team to fix problems found by ESDi” – – Leading RF Chip Company
ESDi simulates multiple ESD triggered devices per event which provides accurate current values on all discharge paths using precise extracted parasitics for the full ESD protection network. EM-violations, high R and IR-drops, device voltage- and current-stress, oxide-breakdown, junction damage, parasitic substrate currents, etc are checked and reported through the user interface or graphically.
The ESDi GUI offers an integrated layout editing tool to help users test and experiment with layout changes to address ESD and current density errors. ESDi makes it easy to change layout and quickly rerun all ESDi analysis and simulation to rapidly find effective fixes for ESD issues. The layout editor tool can be used to change or add metal lines, add or remove vias, and make other layout changes. This time saving ability eliminates tedious iterations that would otherwise be required.