PTM® has an integrated environment that combines a state-of-the-art 3D field solver, an easy-to-use results viewer featuring cross linked reports and field view. Incorporating a proprietary unique edge-based 3D mesher and 64-bit numerical solvers, PTM® extracts Rdson in large power transistor arrays by computing detailed non-uniform current distributions in metal & poly interconnect and vias while including bond wires in the simulation.The tool offers extremely fast simulation on standard Linux workstations with Rdson results matching silicon typically within 2%-5%.
PTM® reports and displays current densities and electro-migration rule violations on the layout. Current density and voltage distributions can be viewed in 2D or cross-cut formats. Designers can focus in on potential trouble spots by locally increasing mesh density for better accuracy. Designers also have full control of terminal placement and excitation, including test benches with Voltage Controlled Current Source (VCVS) to help with high precision sense device design
- 3D extraction and reliability analysis of power semiconductor devices
- Extracts 3D resistance and Rdson
- Extracts current density violations & IR drops
- Generates distributed RC & transistor level netlists
- Supports lateral & vertical DMOS, & IGBT devices
- Imports layout from GDSII
- Supports VCVS for pad stimulus
Power Transistor Modeling Family
PTM® is part of a comprehensive family of tools available from Magwel® for modeling all aspects of power transistor behavior and performance. Designing competitive power devices requires a thorough understanding of timing, transient and electro-thermal behavior of power transistors.
Solving transient behavior in power transistors requires understanding both the metalization and the device physics. PTM-TR™ uses device models in conjunction with its 3D extractor and SPICE solver to provide a complete picture of dynamic device switching behavior.
Switching in power transistors depends on the RC characteristics of the gate metal and poly interconnect in combination with gate oxide and junction capacitance. PTM-GD™ uses a highly accurate solver to extract distributed RC models for the gate interconnect and adds oxide and intrinsic device information. This information is used to predict turn-on time for power transistors that have very large gate widths.
Power transistors generate joule heating in their metal interconnect and device junctions. PTM-ET™ combines this with other heat sources and sinks to determine device thermal behavior over time. There is an interdependence between electrical behavior and thermal behavior, with each affecting the other. PTM-ET™ concurrently and dynamically models devices in their packaging using stimulus to provide an accurate picture during circuit operation over time.