ESD Protection Network Verification Using Magwel’s ESDi for HBM Simulation

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Verifying the Electrostatic Discharge (ESD) protection network on an IC can be challenging, and if it is not done correctly it can lead to failures on the tester, reduced product reliability or shortened field life.

In this webinar you will learn how Magwel’s ESDi thoroughly analyzes all pad combinations in a design for comprehensive ESD protection. Magwel Application Engineer Allan Laser will show how ESDi automatically isolates and extracts the ESD network, including all ESD clamp terminals and then accurately simulates the discharge path(s) between pad pairs.

Chips with large numbers of pins are analyzed extremely quickly by ESDi using parallel processing and optimizations that preserve accuracy and boost speed. Unlike rule-based tools, ESDi uses layout extraction and simulation engines specifically designed for ESD verification to analyze the circuit layout and protection devices. It also does a better job than conventional circuit simulators because they do not handle snapback modeling.

ESDi analyzes multiple ESD device triggering per event which provides accurate current values on all discharge paths using precisely extracted resistive parasitics for the full ESD protection network. User specified voltage and current limits are used to look for violations which are reported through the user interface or graphically.

This webinar includes an overview presentation and tool demo, followed by a Q&A to answer questions about ESDi.