Magwel announces full chip CDM simulation to meet the needs of SOC and advanced process node ASIC designs.
With larger die and package sizes, advanced process nodes and more automated handling of finished chips during assembly and test, CDM looms larger as a source of chip and board failure. While HBM protections are still essential, helping to reduce overall failure rates, we have been hearing from our customers that CDM failures are a top concern. Predicting and accurately simulating CDM failures is not as straightforward as performing pad to pad based HBM simulations.
High voltage across device terminals is identified during CDM event simulation in CDMi
CDM discharges occur after charge builds up on the package and creates capacitively charged metal structures on the die. Once a ground path is created it can be difficult to predict where the current will flow. Current can flow through almost any path in the chip, and consequently reach and potentially damage many devices.
Magwel has developed a unique new tool that builds on our HBM expertise and solves the difficult CDM simulation challenge.
One key advantage of Magwel’s CDM solution is that Magwel CDMi uses dynamic simulation with its FastCDM™ engine. Magwel’s solver based metal characterization engine rapidly sets up and solves all current flows during each pad test. The result is better insight into voltages across protected devices and the currents they are exposed to in the event they trigger.
ESD results for CDM showing discharge event current and voltage across protected device
Magwel’s CDMi features outstanding usability and accuracy. Its ability to model and simulate multiple discharge paths leads to fewer false positives – saving engineers valuable time debugging results. Set up is easy and can be done very quickly. Lastly, viewing errors is made efficient with the fully interactive violation and error reporting view, including links to the layout for violation locations and field views of current density, voltage and more.
Magwel’s new CDMi is built on the established ESDi tool foundation to help improve chip quality and reduce expensive yield loss and field failures.
- Chip-level static and dynamic (transient) simulation of CDM events
- Charge stored on large nets (VSS, VDD, package …)
- Includes capacitive current paths (device-, decoupling- & blocking-caps)
- Computes IR-drops and current densities
- Checks for voltage-stress on protected devices (IO & core)
- Cross-domain checks